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The embedded trace substrate of claim 1, wherein: the at least one signal trace is horizontally positioned along the dielectric layer first surface a first horizontal distance from the first bias trace įurther wherein, the second bias trace is horizontally positioned along the dielectric layer first surface a second horizontal distance from the at least one signal trace įurther wherein, the first horizontal distance and the second horizontal distance are chosen to provide desired electrical properties.
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the at least one signal trace is shaped to optimize electrical performance.The embedded trace substrate of claim 1, wherein the at least one bias trace is shaped to optimize electrical performance.the at least one bias trace depth and at least one signal trace depth are chosen to provide desired electrical properties.The embedded trace substrate of claim 2, wherein the at least one bias trace depth is different from the at least one signal trace depth.The first signal trace and the second signal trace are horizontally positioned along the dielectric layer first surface between the first bias trace and the second bias trace. The at least one signal trace comprises a first signal trace and a second signal trace, further wherein An embedded trace substrate comprising:Īt least one bias trace comprising a first bias trace and a second bias trace, the at least one bias trace being embedded in the dielectric layer such that the at least one bias trace extends an at least one bias trace depth into the dielectric layer Īt least one signal trace horizontally positioned along a dielectric layer first surface between the first bias trace and the second bias trace, the at least one signal trace being embedded in the dielectric layer such that the at least one signal trace extends an at least one signal trace depth into the dielectric layer, wherein the at least one bias trace depth is greater than the at least one signal trace depth and